Round-robin testing and status reviews have led the semiconductor industry to select scanning spreading resistance microscopy (SSRM) and scanning capacitance microscopy (SCM) as their primary methods for carrier profiling. SSRM is generally chosen below the 40 nm lithography node where finer resolution is required. The resolution for SSRM is thought to be as fine as 2.5 nm [K. Arstila, T. Hantschel, C. Demeulemeester, A. Moussa and W. Vandervorst, “Microfabricated diamond tip for nanoprobing,” Microelectron. Eng. 86 (2009) 1222-1225] or even 1 nm [L. Zhang, H. Tanimoto, K. Adachi and A. Nishiyama, “1-nm spatial resolution in carrier profiling of ultrashallow junctions by scanning spreading resistance microscopy,” IEEE Electron Dev. Lett. 29 (2008) 799-801]. However these dimensions are much smaller than the extent of the lattice distortion that is caused by the nanoindentation of the probes which is required in this destructive process [K. Mylvaganam, L. C. Zhang, P. Eyben, J. Mody and W. Vandervorst, “Evolution of metastable phases in silicon during nanoindentation: mechanism analysis and experimental verification,” Nanotechnology 20 (2009) 305705] so it is possible that the results may not be an accurate characterization of the semiconductor.
New technology is required as the semiconductor industry progresses to finer lithography nodes for progress to new devices having improved performance in accordance with Moore's law. The first commercial products containing devices at the 22 and 14 nm nodes were introduced in 2012 and 2014, respectively. On Jul. 9thof 2015 an alliance led by IBM Research announced production of the first 7 nm node test chips with functioning transistors. This step was made ahead of schedule because it had not been expected to occur until 2018-2019. Thus, even with SSRM, the rule-of-thumb in roadmaps for the semiconductor industry that the resolution for carrier profiling should be finer than 10% of the lithography node cannot be met now at the 7 nm node, or at the 5 nm and 2 nm nodes for which research is already in progress. To summarize, accurate carrier profiling with a resolution of 0.7 nm is now required at the 7 nm node and a resolution of 0.5 nm and 0.2 nm will be required at the 5 nm and 2 nm lithography nodes.
Unusually high carrier densities are required at the new lithography nodes. An approximate lower bound for the required majority carrier density c may be set by requiring that a sphere with radius r must contain at least 1 carrier so that 4πr3c/3>1, or c>3/4πr3 where r is the dimension of the respective lithography node. Thus, c must be greater than 2.4×1017, 7.0×1017, 1.9×1018, and 3.0×1019/cm3 at the 10 nm, 7nm, 5 nm, and 2 nm nodes.
Inherent Limit for the Resolution in Scanning Capacitance Microscopy:
In SCM a semiconductor is coated with a thin layer of oxide and a small metal tip is scanned across this surface. A bias voltage is applied to the tip to cause a depletion region immediately below the surface of the semiconductor and small changes in the capacitance of the depletion region are measured as this bias is varied. The carrier profile is determined from the derivative of the capacitance in respect to the bias voltage, dC/dV. This may be understood because an incremental change in the voltage causes an incremental change in the thickness of the depletion region which changes the capacitance, and the change in the thickness is proportional to the carrier density. Measurements show that the resolution with SCM is no finer than 15 nm [P. Eyben, N. Duhayon, D. Alvarez and W. Vandervorst, “Assessing the resolution limits of scanning spreading resistance microscopy and scanning capacitance microscopy,” Proceedings of the International Conference on Characterization and Metrology for ULSI Technology, 2003, pp. 678-684]. This limitation may be understood because the measured capacitance includes fringing between the base of the depletion layer and the shank and connections to the tip. In this proposed application of scanning tunneling microscopy, the tunneling current decreases exponentially with distance whereas capacitance is proportional to the reciprocal of distance. Thus, this new method is not sensitive to the presence of the shank and the connections to the tip.
Inherent Limit For the Resolution in Scanning Spreading Resistance Microscopy:
The concept of electrical resistance is only valid when the carriers in a semiconductor travel distances that are three or more times the mean-free-path λ(λ≈10 to 100 nm) in order to have several scattering events. At shorter distances the carriers have only ballistic motion as they spread away from their source by diffusion caused by their differences in velocity, with the additional effects of electrical interaction. Thus, it is not clear how carrier profiling based on electrical resistance could have a resolution as fine as 2.5 nm or 1 nm. Scanning spreading resistance microscopy measurements may actually have several different mechanisms. For example, in carrier profiling by SSRM the ideal relation for spreading resistance, R=ρ/4a (where ρ is the resistivity and a is the radius of a circular contact), is replaced by the nonlinear relation R=f(ρ) requiring calibration with standard samples [P. Eyben, M. Xu, N. Duhayon, T. Clarysse, S. Callewaert and W. Vandervorst, “Scanning spreading resistance microscopy and spectroscopy for routine and quantitative two-dimensional carrier profiling,” J. Vac. Sci. Technol. B 20 (2002) 471-478]. Examples of calibration curves, log-log plots of the measured resistance vs. the known resistivity, are irregular with a mean slope of 0.6 for n-type structures. Furthermore, the contact between the probe and the semiconductor is not ohmic so current vs. voltage plots are nonlinear, and the measurements are also sensitive to surface states in the semiconductor [P Eyben, S. Denis, T. Clarysse and W. Vandervorst, “Progress towards a physical contact model for scanning spreading resistance microscopy,” Mat. Sci. Engineering B 102 (2003) 132-137].
Previous uses of a Microwave Frequency Comb
The previous art pertaining to the use of a Microwave Frequency Comb (MFC) for characterizing semiconductors relates to two different methods, SCM and SSRM, which were previously used without the MFC and thus they have different inherent limits for their resolution.
(1) Depletion capacitance—U.S. Pat. No. 5,065,103 describes how to make electrical measurements of the depletion capacitance in order to determine the carrier concentration (though they claim dopant concentration) prior to the discovery of the MFC. More recently U.S. Pat. No. 8,601,607 describes how to measure the attenuation of the MFC with a reverse biased semiconductor. Thus a depletion layer is formed in the semiconductor and the effect of the depletion capacitance on the attenuation of the MFC is used to determine the carrier concentration (though it also claims dopant concentration). The resolution using this method would be limited by the fringing capacitance between the base of the depletion layer and the shank and connections to the tip as it is in SCM.
(2) Spreading resistance—U.S. Pat. No. 5,585,734 describes how to measure the spreading resistance to determine the carrier concentration prior to the discovery of the MFC. U.S. Published application 2015/0247809 describes how to use a MFC to measure the attenuation of the MFC, which is caused by the spreading resistance in order to determine the carrier concentration. However, it is noted that measurements of any resistance have an inherent limitation for their resolution.